/*
 * @[H]:  Copyright (c) 2021 Phytium Information Technology, Inc. 
 * 
 *  SPDX-License-Identifier: Apache-2.0. 
 * 
 * @Date: 2021-07-12 17:20:40
 * @LastEditTime: 2021-07-15 14:49:13
 * @Description:  Description of file
 * @Modify History: 
 * * * Ver   Who        Date         Changes
 * * ----- ------     --------    --------------------------------------
 */

#ifndef BSP_DRIVER_GPIO_F_GPIO_HW_H
#define BSP_DRIVER_GPIO_F_GPIO_HW_H

#ifdef __cplusplus
extern "C"
{
#endif

#include "parameters.h"
#include "ft_io.h"

#define GPIO_SWPORTA_DR_OFFSET 0x00  /* WR Port A Output Data Register */
#define GPIO_SWPORTA_DDR_OFFSET 0x04 /* WR Port A Data Direction Register */
#define GPIO_EXT_PORTA_OFFSET 0x08   /* RO Port A Input Data Register */
#define GPIO_SWPORTB_DR_OFFSET 0x0c  /* WR Port B Output Data Register */
#define GPIO_SWPORTB_DDR_OFFSET 0x10 /* WR Port B Data Direction Register */
#define GPIO_EXT_PORTB_OFFSET 0x14   /* RO Port B Input Data Register */

#define GPIO_INTEN_OFFSET 0x18         /* WR Port A Interrput Enable Register */
#define GPIO_INTMASK_OFFSET 0x1c       /* WR Port A Interrupt Mask Register */
#define GPIO_INTTYPE_LEVEL_OFFSET 0x20 /* WR Port A Interrupt Level Register */
#define GPIO_INT_POLARITY_OFFSET 0x24  /* WR Port A Interrupt Polarity Register */
#define GPIO_INTSTATUS_OFFSET 0x28     /* RO Port A Interrupt Status Register */
#define GPIO_RAW_INTSTATUS_OFFSET 0x2c /* RO Port A Raw Interrupt Status Register */
#define GPIO_LS_SYNC_OFFSET 0x30       /* WR Level-sensitive Synchronization Enable Register */
#define GPIO_DEBOUNCE_OFFSET 0x34      /* WR Debounce Enable Register */
#define GPIO_PORTA_EOI_OFFSET 0x38     /* WO Port A Clear Interrupt Register */

    /***************** Macros (Inline Functions) Definitions *********************/

#define FGPIO_READREG32(addr, reg_offset) FtIn32(addr + (u32)reg_offset)

#define FGPIO_WRITEREG32(addr, reg_offset, reg_value) FtOut32(addr + (u32)reg_offset, (u32)reg_value)

#ifdef __cplusplus
}
#endif

#endif // !
